The present disclosure relates generally to the fabrication of semiconductor devices, and more particularly, to a method and system for the removal of photoresist residue from a semiconductor wafer.
Semiconductor device geometries have dramatically decreased in size since such devices were first introduced several decades ago. Since then, integrated circuits have generally followed the two year/half-size rule (often called Moore's Law), which means that the number of devices on a chip doubles every two years. Today's fabrication plants are routinely producing devices having 0.35 micron and even 90 nm feature sizes.
Due to the ever shrinking design rules, changes have been made throughout the semiconductor manufacturing process. For example, strategies to minimize interconnect delays involve improving conductivity with copper wiring and lowering the dielectric constant (k) value by employing low k films. While copper integration is fairly advanced, low k materials present a wide range of new integration challenges because of their lower density, inferior mechanical properties, and typically increased organic content. In dual damascene applications, they are layered between a variety of other films. The number of stack combinations and requirements necessitate developing processes and process systems that are highly flexible and provide large processing windows.
Therefore, there is a need for an improved deposition process and reactor configuration that improves the uniformity of thin films produced by IMP.